This invention relates to metallization processes of particular utility in integrated semiconductor device and circuit board manufacture, which processes employ "damascene" (or in-laid) technology.
With reference to FIG. 1, schematically shown therein in cross-sectional view is a conventional damascene processing sequence for forming recessed metallization patterns ("back-end" contacts, vias, interconnections, etc.) in semiconductor devices formed in or on a semiconductor wafer substrate 1. In a first step, the desired conductor pattern is defined as a pattern of recesses 2 such as grooves, trenches, holes, etc. in a dielectric layer 3 formed over the semiconductor substrate, followed by a second step comprising deposition of a suitably conductive metal layer 5 filling the etched recesses 2. Typically, in order to ensure complete filling of the recesses, the metal layer 5 is deposited as a blanket layer of excess thickness t so as to overfill the recesses 2 and cover the upper surface 4 of the dielectric layer 3. Next, the entire excess thickness t of metal layer 5 over the surface of the dielectric layer 3 is removed using a CMP process, leaving metal portions 5' in the recesses with their upper (i.e., exposed) surfaces 6 substantially coplanar with the surface 4 of the dielectric layer. Thus this process, termed "damascene process", forms in-laid conductors in the dielectric layer while avoiding problems associated with types of other processes, e.g., metal etching and dielectric gap filling.
While such damascene processing can be performed with a variety of other types of substrates, e.g., printed circuit boards, with and/or without intervening dielectric layers, and with a number of metallization materials, including copper, aluminum, gold, silver, and their alloys, the parallel drives toward cost reduction and increased microminiaturization of semiconductor devices have provided an impetus for greater utilization of copper or copper alloy-based interconnection metallurgy, particularly in view of the attendant low resistivity and ability to reliably carry high current densities. However, the use of copper-based metallurgy has presented several problems, including the possibility of diffusion into the semiconductor substrate and poor adhesion to various dielectric materials, necessitating provision of an adhesion/barrier layer (e.g., chromium, tantalum, tantalum nitride) prior to depositing copper-based metallization.
Another problem associated with damascene processing of copper-based interconnection metallurgy arises from the use of electrolytic deposition of the copper material for filling vias, trenches, etc., followed by CMP to remove the excess copper. Electroplating has advantages, such as rapid deposition rates vis-a-vis "dry" processes, such as physical or chemical vapor deposition, and good compatibility with "wet" CMP processing which minimizes or eliminates difficult, expensive, and time consuming switchover from dry to wet process technology. However, electrolytic deposition of copper suffers from the drawback of ridge build-up over sharp corners of vias, grooves, and trenches. Thus, in conventional practices utilizing electrolytic deposition, a rather thick blanket layer 5 of copper, typically from about 0.5 u to about 1.5 u thick, is deposited over the recess-patterned surface to ensure complete filling (i.e., overfilling) of recesses 2 such as via holes, trenches, grooves, and other shapes of varying dimensions. Moreover, the resulting surface after overfilling is highly non-planar and, consequently, the layer thicknesses thereof may span the entire range of thicknesses given above.
Removal of such thick, non-planar blanket layers of copper in the subsequent CMP step for planarizing the interconnection metallization entails a number of drawbacks. First, CMP of copper or copper-based alloys is slow and expensive. Specifically, typical copper removal rates by CMP employing a conventional alumina-based slurry are on the order of about 2,000-3,000 angstroms/min. Consequently, removal of 0.5 u-1.5 u thick copper layers can require long processing times extending up to about 5 minutes, considerably longer than that desired for good manufacturing throughput and reduced expense. Second, in general, and in particular for copper-based layers subjected to CMP, removal of such thick as-deposited layers results in less uniform polished layers as are obtained when CMP is performed on thinner deposited layers. Third, such poor uniformity is generally accompanied by an increase in defects such as non-planarity ("dishing") and gouging ("erosion") between adjacent metallization lines.
Thus, there exists a need for a method for forming in-laid metallization patterns by a damascene technique which does not suffer from the problems of the prior art, i.e., reduced manufacturing throughput, increased cost, poor uniformity, and increased occurrence of defects such as "dishing" and "gouging". Specifically, there exists a need for an improved CMP-based metallization method for forming copper-based "back end" in-laid contacts and interconnection routing of transistors in integrated circuit semiconductor devices. Moreover, there exists a need for an improved CMP-based method for forming such contacts and interconnections which is fully compatible with conventional process flow and methodology in the manufacture of such integrated circuit semiconductor devices and other devices requiring in-laid metallization patterns.